1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to the manufacture of metallization layers including conductive materials, such as copper, embedded into a dielectric material.
2. Description of the Related Art
In an integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of advanced integrated circuits, the electrical connections of the individual circuit elements are generally not established within the same level on which the circuit elements are manufactured. Typically, such electrical connections are formed in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, that are filled with an appropriate metal. Thus, the vias provide the electrical connection between two neighboring stacked metallization layers, wherein the metal-containing lines and vias may also be commonly referred to as interconnect structures.
Due to the continuous reduction of feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the packing density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers may increase and the dimensions of the individual lines and vias may be reduced as the number of circuit elements per chip area becomes larger. The vias may typically be formed by etching an opening into a respective interlayer dielectric material, which, in sophisticated applications, may be a low-k material in combination with a highly conductive metal, such as copper or copper alloys, and subsequently filling the opening with an appropriate conductive material. Due to the reduced dimensions of the vias, sophisticated anisotropic etch techniques are usually necessary for forming the high aspect ratio openings.
It turns out that the process of etching vias in the dielectric layer may significantly affect the overall production yield during the formation of advanced semiconductor devices owing to substrate damage caused by plasma-assisted etch processes.
With reference to FIG. 1, a typical conventional process flow will now be described in more detail, wherein via openings for a metallization structure of an advanced semiconductor device are formed on the basis of a plasma-assisted etch process.
FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, which may be provided in the form of a bulk silicon substrate, a silicon-on-insulator (SOI) substrate and the like, wherein the substrate 101 may also represent a device layer having formed therein individual circuit elements, such as transistors, capacitors, contact portions and the like. For convenience, in FIG. 1, a respective layer 102 is illustrated as representative of any circuit elements or contact portions to which a vertical electrical connection is to be formed, as will be described later on in more detail. The layer 102 may, for instance, be comprised of any appropriate dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride and low-k dielectric materials, wherein a low-k dielectric material is to be understood as a material having a dielectric constant that is 3.0 or less. For example, the layer 102 may represent a portion of a metallization structure of the device 100, in which may be formed respective metal regions 103, 104, which may represent metal lines, extended metal regions and the like, depending on the device requirements. The metal regions 103, 104 may be comprised of any appropriate material, such as copper, copper alloys or combinations of various different materials, wherein typically conductive barrier materials may be provided, especially when copper-based metal regions are considered. For example, the metal regions 103, 104 may differ in their lateral dimensions depending on the corresponding device design. It should be appreciated that other circuit elements, such as semiconductor devices and the like, may be formed in any appropriate device layer located below the layer 102. Furthermore, an etch stop layer 105 may be provided on the layer 102, followed by a dielectric layer 106, such as a low-k dielectric layer, when sophisticated semiconductor devices are considered, in which any parasitic capacitance between neighboring metal regions is to be reduced. In other cases, the dielectric material of the layer 106 may comprise other appropriate materials, such as silicon dioxide, silicon nitride, silicon oxynitride, fluorine-doped silicon dioxide and the like. More-over, a respective anti-reflective coating (ARC) layer 107 may be formed on the dielectric layer 106 followed by a resist mask 108. Furthermore, in the manufacturing stage shown in FIG. 1, respective openings 109A, 109B may be partially formed in the dielectric layer 106, wherein these openings 109A, 109B in this example may have to extend into the respective metal regions 103, 104 in order to provide an electrical connection, for instance, for a further metallization layer to be formed above the dielectric layer 106.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1 may comprise the following processes. After manufacturing respective semiconductor elements (not shown) in one or more appropriate semiconductor layers formed above the substrate 101, the dielectric layer 102 may be formed on the basis of well-established deposition techniques, such as chemical vapor deposition (CVD) wherein a plurality of recipes are established for various materials. Thereafter, the metal regions 103, 104 may be formed on the basis of appropriate etch techniques followed by respective metal deposition processes, such as CVD, electrochemical techniques and the like. Next, the etch stop layer 105 may be formed on the basis of a CVD process, wherein the material composition of the etch stop layer 105 may also be selected in view of a reliable confinement of the metal in the regions 103 and 104. Then, the dielectric layer 106 may be formed on the basis of any appropriate deposition technique for providing the dielectric material having the desired characteristics. Thereafter, well-established lithography processes may be performed, which may include the deposition of the ARC layer 107 having optical characteristics so as to avoid undue back reflection of exposure radiation used for selectively exposing the resist layer 108, which may be formed on the ARC layer 107 on the basis of spin-on techniques in order to form a respective etch mask.
After the patterning of the resist layer 108, an anisotropic etch process 110 may be performed in order to etch into the dielectric layer 106 on the basis of the overlying patterned resist layer 108 and the patterned ARC layer 107. Typically, the etch process 110 has to exhibit a highly anisotropic behavior due to the moderately low lateral dimensions required for the openings 109A, 109B for a given thickness of the layer 106. Thus, well-established plasma-assisted recipes are used for the process 110, wherein, in a typical plasma-based etch process, reactive ions are created and are accelerated towards the substrate 101 in order to obtain a high directionality for providing a moderately high physical component, which is substantially oriented perpendicular to the surface of the device 100. Furthermore, respective polymer materials may be added to the etch ambient of the process 110 in order to appropriately reduce a lateral etching, while substantially not affecting the vertical progress of the corresponding etch front.
Due to the highly complex conditions within the plasma etch ambient, increasingly positive ions may accumulate in a lower portion of the respective openings 109A, while negative charge may accumulate in an upper portion thereof, thereby increasingly building up a vertical potential difference. Consequently, due to the highly local separation of positive and negative charges, a highly localized potential difference may be created in the vicinity of the respective openings 109A, 109B wherein, under certain conditions, a so-called arcing event may occur when the potential difference rises to a critical value. During the arcing, burnt metal and “worm-like” arcing marks may be created, thereby resulting in a significant loss of production yield, as corresponding arcing events may render the respective device unusable. Thus, the frequency of arcing events may significantly affect the yield per substrate, wherein, however, the occurrence of arcing events is difficult to predict, wherein experience indicates that plasma instabilities and surface structure conditions, such as pattern density, the presence of lower lying metal regions and the like, may have a significant influence. For instance, the frequency of arcing events during dielectric etch processes may be extremely low in the absence of lower lying metal regions, whereas a significant increase of the frequency of arcing events may be observed during the formation of metallization structures of sophisticated semiconductor devices. In particular, during the formation of respective via openings, such as the openings 109A, 109B, a high probability for the occurrence of arcing events may be observed especially, if higher laying metallization layers are involved. Furthermore, as is illustrated in FIG. 1, the local charge separation occurring at the different openings 109A, 109B may not be identical, since the corresponding etch conditions may vary locally, for instance due to a different device configuration in the vicinity of the respective openings, such as the differently sized metal regions 103, 104 and the like. For instance, in the example shown, a plurality of laterally spaced openings, such as the opening 109A, may be formed with a moderately low degree of charge separation, while the opening 109B may build up, due to a locally different environment, a moderately high potential difference, thereby significantly increasing the probability for an arcing event, which may then result in a total loss of the entire device 100, even though a high number of less critical openings 109A may be commonly formed with the opening 109B. Consequently, a significant yield loss may occur at a moderately late stage of the manufacturing process flow for forming the device 100 due to plasma-induced damage.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.